Analog requirements to integrate on the same chip high density logic with high voltage, high power devices has led to the wide acceptance of dual gate (split gate) technologies. In addition, continuous scaledown demands have resulted in increased aspect ratios for shallow isolation trenches (STI) between active devices. Atmospheric-pressure chemical vapor deposition (APCVD) has met the isolation demands for technologies with gate lengths greater than 0.5 um, but for smaller technologies with higher STI aspect ratios, high density plasma deposition process has been used instead.
HDP provides much better fill for shallow isolation trenches when higher STI aspect ratios are present like technologies with gate length less than 0.5 um. However, the semiconductor manufacturing industry has since learned that the HDP is a higher stress material, and as a result, oxide thinning occurs on the corners of the active regions. Moreover, the additional stress placed on the walls of the isolation trenches causes a number of other silicon defects, thereby increasing defect densities of various devices.